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Accelerating Nested Conditionals on CGRA With Tag-Based Full Predication Method
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DOI：10.1109/ACCESS.2020.3001220.png)
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Abstract
En 中文
CGRA (Coarse-grained Reconfigurable Architecture) has been widely considered as one of the most promising computing architectures to exploit spatial parallelism. Compared with the typical general-purpose architectures which are instruction-driven, most of the state-of-art CGRAs are designed following the data-driven strategy, leading to difficulties while dealing with control-flow (nested if-then-else structures, NITE). Tackling with this problem, existing techniques such as partial predication and full predication introduce extra conditional move and select operations, while state-based full predication (SFP) introduces sleep and awake operations to correctly implement the basic function of NITE. Meanwhile, performance degradation is also incurred by these redundant operations. In this paper, a novel tag-based full predication (TFP) strategy is proposed, trying to eliminate redundant operations and thus accelerate NITE on CGRAs. The extra tag field is added to each instruction word to implement distributed nullification and parallel tag register (TReg) overwriting. Hardware support for TFP is present, and experimental validation is based on RTL-level simulation with manual mapping. Results show that our method achieves over 30% performance gain on average compared with SFP at the expense of around 5% additional power consumption and ignorable area overhead.
Keywords:
Registers
Acceleration
Computer architecture
Routing
Parallel processing
Hardware
Power demand
Reconfigurable architectures
control-flow
nested branch
full predication
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