Adaptive 2-D Scheduling-Based Nonbinary Majority-Logic Decoding for NAND Flash Memory

doi:10.1109/TCSII.2019.2935031

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Adaptive 2-D Scheduling-Based Nonbinary Majority-Logic Decoding for NAND Flash Memory

2020-07-01

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DOI：10.1109/TCSII.2019.2935031

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Abstract

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This brief presents a nonbinary adaptive 2D scheduling-based majority logic decoding (NB-ATS-MLGD) algorithm for NAND flash memory. The proposed algorithms provide considerable tradeoff between error-correcting capability and decoding complexity, and make the NB-MLGD decoding more attractive for practical purposes in the multi-level cells (MLC) NAND flash memory. The most significant feature of the proposed NB-ATS-MLGD algorithm is the 2D layered scheduling strategy, where the decoding orders of check nodes (CNs) and variable nodes (VNs) are both adaptive. By leveraging on the MLC flash memory bit error patterns, an early-correcting (EC) criterion is incorporated into the NB-ATS-MLGD algorithm. Furthermore, the simplification and parallelization of proposed algorithms make them more practical in NAND flash memory. Simulation results show that the proposed algorithms increase the lifetime of MLC flash memory up to 3000 program-and-erase (PE) cycles and have desirable convergence speed compared with the conventional non-binary MLGD algorithm. When at low PE cycles, the NB-EC-ATS-MLGD algorithm improves frame error rate (FER) performance by more than 3 order of magnitudes compared with the conventional non-binary MLGD algorithm.

Keywords:

Decoding

Reliability

Two dimensional displays

Message passing

Complexity theory

Iterative decoding

Scheduling

Multi-level cell (MLC)

NAND flash memory

non-binary low-density parity-check (NB-LDPC) codes

2D scheduling

majority-logic decoding (MLGD)

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