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Adiabatic Logic Based Energy-Efficient Security for Smart Consumer Electronics
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DOI：10.1109/MCE.2020.3028046.png)
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Abstract
En 中文
Smart consumer electronic devices are mostly area constrained and operate on a limited battery supply and therefore, have tight energy budgets. Lightweight cryptography (LWC) such as PRESENT-80 allows for minimal area usage and low energy for secure operations. However, CMOS implemented LWCs are vulnerable to side-channel attacks such as correlation power analysis (CPA). Adiabatic logic is an emerging circuit design technique that can reduce energy consumption and be CPA resistant. Many existing adiabatic logic families use a four-phase clocking scheme which pays a large area penalty. Thus, in this article, we introduce 2-EE-SPFAL, a two-phase clocking scheme implementation of an existing adiabatic family known as EE-SPFAL. To show the applicability of 2-EE-SPFAL, we construct a two-phase clock generator that remains energy efficient and secure. From 100 kHz to 25 MHz, our results show an average energy saving of 76.5% to 21.3% between CMOS and 2-EE-SPFAL. As a case study, we performed a CPA attack on both the CMOS and 2-EE-SPFAL implementation of PRESENT-80 and determined that the CMOS key could be retrieved while the adiabatic key was kept hidden.
Keywords:
Clocks
Adiabatic
Discharges (electric)
Generators
Consumer electronics
Logic gates
Security
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