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Advanced Signal Processing Technique for Storage Systems
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DOI：10.1109/TCE.2010.5681114.png)
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Abstract
En 中文
A post-Viterbi processor has found wide acceptance in recording systems since it can correct dominant error events at the channel detector output using only a few parity bits, and thereby significantly reduce the correction capacity loss of the error correction code. This paper presents two novel techniques for minimizing the mis-correction of a post-Viterbi processor based on an error detection code. One is a method for achieving a low probability of mis-selection in actual error-type. The other is a method for achieving a low probability of mis-positioning in error-location of an occurred error event. Simulation results show that an application of these techniques to conventional post-Viterbi processor considerably reduces the probability of mis-correction and the performance approaches the corresponding bit error rate and symbol error rate bound.
Keywords:
Error detection code
dominant error event
matched-filtering type post-Viterbi processor
cyclic redundancy check code
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