Advanced task scheduling algorithm for enhanced energy efficiency on multi-core embedded platforms

B. Saravanakrishnan

doi:10.1016/j.compeleceng.2025.110886

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Advanced task scheduling algorithm for enhanced energy efficiency on multi-core embedded platforms

2025-12-05

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B. Saravanakrishnan

G.R. Jeshnu Skandan

B. Naresh Kumar Reddy *

DOI：10.1016/j.compeleceng.2025.110886

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Abstract

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Energy consumption minimization is one of the essential requirements in scheduling tasks in heterogeneous multicore embedded systems in which Dynamic Voltage and Frequency Scaling (DVFS) plays a significant role. Using techniques like DVFS helps to achieve better task scheduling, but the problem of task scheduling becomes an NP-Hard problem. To address these problems, our work proposes a novel approach to assigning frequencies to each task and allocating tasks to various cores in a multicore processor. Our method introduces a less complex yet energy-efficient frequency assignment and task allocation strategy. The Frequency Assignment (FA) algorithm uses the binary search for frequency selection, which reduces the computational complexity to O(N⋅logL), where N is the number of tasks and L represents the frequency levels. This guarantees that the frequency is allocated to each task optimally and consumes less energy. For task allocation, we proposed a Task Assignment (TA) algorithm based on Rank and Earliest Finish Time (EFT), which ensures that the tasks are assigned to available processor cores to minimize the overall execution time of the processor. This strategy minimizes energy consumption, distributes the workload evenly, and efficiently uses the available processing power. We compare our solution with other energy-efficient algorithms to evaluate performance in various applications like Gaussian Elimination (GE) and random task graph. Our numerical results demonstrate that the proposed scheduling algorithms perform significantly higher than the existing energy-efficient algorithms in terms of energy savings, task execution efficiency, and reduced computation complexity. The proposed work is implemented in Verilog on the Zynq Ultrascale＋ MPSoC ZCU106 Evaluation Kit FPGA platform, and its performance has been validated.