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AHB Interconnect - Functional Verification
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DOI：10.59277/ROMJIST.2023.3-4.04.png)
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Abstract
En 中文
This paper offers an in-depth exploration of the verification procedure pertaining to the integration of an Advanced High-performance Bus (AHB) Interconnect module. The verification process holds pivotal significance within chip development, entailing thorough validation and examination of the hardware design before entering the mass production phase. The principal objective of this verification process is to meticulously unearth potential bugs or imperfections embedded in the design, which could potentially trigger undesirable outcomes, compromised performance, or even critical malfunctions in the final product. At the heart of this verification approach lies the functional verification paradigm, centered around simulation-based testing. Within this framework, the AHB Interconnect module is instantiated in a controlled verification environment designed to emulate real-world scenarios. This environment orchestrates input stimuli to the module and captures ensuing outputs generated by it. The environment is meticulously programmed to anticipate specific behavioral patterns from the module. Deviations from these anticipated behaviors are promptly flagged as errors. This meticulous methodology serves to guarantee that the module aligns with its intended operations and strictly adheres to predefined functional benchmarks. The paper is dedicated to Acad. Florin Gheorghe Filip, at his 15(th) anniversary as the Chairman of the Information Science and Technology Section of the Romanian Academy, and at his 75(th) anniversary.
Keywords:
AHB
Interconnect
Functional verification
Protocol compliance
Concurrency
Arbitration
Master devices
Slave devices
Stimuli and responses
Simulation
Journal
R
IF:
3.9
Papers:
26
Citations:
442
Organization
Cited Papers