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ALAG: A Silicon-Proven, Non-Fixed-Grid Framework for Hierarchical Analog Layout Automation
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DOI：10.1109/tcsi.2026.3702661.png)
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Abstract
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Physical design remains a critical bottleneck in Analog/Mixed-Signal (AMS) chip development, particularly for hierarchical designs containing pre-designed macro-blocks. In such scenarios, existing unified fixed-grid layout generation frameworks face a fundamental geometric incompatibility with arbitrary IP pin locations. To address this, this paper presents ALAG: a non-fixed-grid framework for hierarchical analog layout automation. ALAG operates through the synergy of three core modules: a rule-driven gridless device generator, a constraint-aware reinforcement learning placement engine, and a dynamic-grid A* router. Experiments on multiple industrial-grade circuits demonstrate that ALAG achieves zero Design Rule Check (DRC) violations and 100% Layout Versus Schematic (LVS) consistency. Notably, for a complex Near-Field Communication Analog Front-End (NFC-AFE) system containing over 6,000 transistors, the framework automatically completes layout generation in just 0.6 hours. Fabricated in a 180 nm process, the chip achieves electrical performance and functional robustness comparable to expert manual designs, validating ALAG as a practical solution for complex, macro-centric AMS silicon implementation.
Keywords:
Analog layout automation
silicon-proven
macro-block integration
non-fixed-grid
hierarchical design
reinforcement learning
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