.png){kind=icon}
Return
Algorithm Level Error Detection in Low Voltage Systolic Array
.png){kind=icon}
OA
AI
DOI：10.1109/TCSII.2021.3094923.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
In this brief an approach is proposed to achieve energy savings from reduced voltage operation. The solution detects timing-errors by integrating Algorithm Based Fault Tolerance (ABFT) into a digital architecture. The approach has been studied with a systolic array matrix multiplier operating at reduced voltages, detecting errors on-the-fly to avoid energy demanding memory round-trips. The analysis of the solution has been done using analog-digital co-simulation to extract the transient behavior under different voltages and clock frequencies. HSPICE simulations using 90nm CMOS transistor models, and experiments by reducing operation voltage of an FPGA device were carried out. HSPICE simulations, showed possibility of 10x increase in energy-efficiency by approaching near-threshold region.
Keywords:
Energy efficiency
low power
matrix multiplier
FPGA
accelerator
near threshold
Journal
I
IF:
4.9
Papers:
8.8K
Citations:
2.5W
Organization
Cited Papers
ShareSaveShareSaveA Sub-μW Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications
OAAI
OAAIShareSaveStereocomplex crystallization of equimolar Poly(L-lactic acid)/Poly(D-lactic acid) blends from melt with lowered chain entanglements.png)
Polymer
PolymerIF0
PREAI
ShareSaveInjection of ROS-Responsive Hydrogel Loaded with IL-1(3-targeted nanobody for ameliorating myocardial infarctionBIOACTIVE MATERIALS
BIOACTIVE MATERIALSIF20.3
PREAI
ShareSaveShareSaveShareSave
View more