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An Area-Efficient and Low-Error FPGA-Based Sigmoid Function Approximation
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DOI：10.3390/app152111551.png)
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Abstract
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Neuromorphic hardware systems allow efficient implementation of artificial neural networks (ANNs) across various applications that demand high data throughput, reduced physical size, and low energy consumption. Field-Programmable Gate Arrays (FPGAs) possess inherent features that can be aligned with these requirements. However, implementing ANNs on FPGAs also presents challenges, including the computation of the neuron activation functions, due to the balance between resource constraints and numerical precision. This paper proposes a resource-efficient hardware approximation method for the sigmoid function, utilizing a combination of first- and second-degree polynomial functions. The method aims mainly to minimize the approximation error. This paper also evaluates the obtained results against existing techniques and discusses their significance. The experimental results showed that, although the proposed method mainly aimed to minimize the approximation error, it also had lower hardware resource usage than several of the most closely related works. Using 16-bit fixed-point number representation, the absolute mean error was 1.66x10-3 by using 0.04% of the logic blocks and 3.21% of the DSP blocks in a Ciclone V 5CGXFC7C7F23C8 FPGA Device.
Keywords:
neuromorphic hardware
Field-Programmable Gate Array
artificial neural network
neuron activation function
sigmoid
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