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An Area-Efficient, High-Throughput 2T-2MTJ STT-MRAM Architecture for In-Memory Computing Applications
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DOI：10.1109/TNANO.2026.3681441.png)
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Abstract
En 中文
This paper presents a novel 2T-2MTJ STT-MRAM bit-cell architecture tailored for In-Memory Computing (IMC) applications, designed to address the limitations of conventional memory architectures. Using 2T-2MTJ bit-cells, our design significantly reduces chip area compared to traditional 8Transistor/10Transistor SRAM bitcell architectures while maintaining high throughput and energy efficiency. A tunable clamp voltage sensing scheme is introduced, enabling parallelism and efficient execution of key bitwise operations such as XNOR, NOR, and NAND without the added complexity of Analog-to-Digital Converters (ADC). Benchmarking using NeuroSim with the VGG-8 neural network, trained on the CIFAR-10 dataset, revealed a 208.52% and 95% increase in throughput (measured in TOPS) compared to 10T SRAM and 1T-1MTJ architectures, respectively, along with improvements in chip area, clock frequency, and overall system performance. This work showcases the potential of STT-MRAM-based IMC architectures to enhance energy efficiency, reduce design complexity, and improve scalability for Artificial Intelligence (AI) / Machine Learning (ML) workloads, making it a promising solution for next-generation computing systems.
Keywords:
Feeds
Antennas
Circuits
Circuits and systems
Circuit synthesis
Integrated circuits
System-on-chip
Very large scale integration
Adders
Application specific integrated circuits
AI
CIFAR-10 dataset
VGG-8
SRAM bitcell
MTJ
STT-MRAM
in-memory computing
Journal
I
IF:
2.5
Papers:
37
Citations:
3.8K