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An Area-Efficient Normal Input/Output Ordered Memory-Based FFT Using an SC Kernel
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DOI：10.1109/TCSII.2025.3645948.png)
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Abstract
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This brief presents a 1024-point radix-2 memory-based fast Fourier transform (FFT) architecture. This work aims to achieve a normal order at both the input and the output without requiring an additional circuit or memory. The proposed architecture is the first memory-based FFT to utilize a serial commutator (SC) kernel as a processing element (PE). This halves the number of adders and multipliers. Likewise, a novel address generation circuit is presented. It produces the same memory read and write addresses for both memories, as well as conflict-free access. The proposed architecture has been implemented on a Virtex 7 field-programmable gate array (FPGA). The experimental results indicate that it achieves low area, efficient resource utilization, and low power consumption.
Keywords:
FFT
memory-based
normal I/O order
SC
radix-2
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