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An efficient bit-wise iterative stochastic decoder for turbo product codes
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DOI：10.1016/j.dcan.2026.07.009.png)
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Abstract
En 中文
Turbo Product Codes (TPCs) are increasingly considered efficient Forward Error Correction (FEC) schemes in modern high-speed communication systems. A key obstacle to their implementation lies in the design of a low-complexity decoder architecture. While recent soft-decision decoders commonly adopt Chase or Belief Propagation (BP) algorithms, this work introduces an alternative bit-wise iterative decoding approach along with its corresponding hardware structure, aiming to minimize decoding complexity and enhance hardware efficiency. Additionally, a set of innovative techniques for lowering complexity and accelerating convergence is presented. Both performance simulations and implementation outcomes confirm that the proposed architecture not only attains considerable reductions in complexity and gains in hardware efficiency, but also shows marginally improved error correction performance relative to prior solutions. These attributes position the design as a viable option for practical high-throughput communication hardware.
Keywords:
Error-correction codes
Turbo product codes
Iterative decoding
Stochastic decoding
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