An efficient multi-format low-precision floating-point multiplier

Hadis Ahmadpour Kermani

doi:10.1016/j.suscom.2023.100928

An efficient multi-format low-precision floating-point multiplier

2024-01-01

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Hadis Ahmadpour Kermani

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Azadeh Alsadat Emrani Zarandi *

DOI：10.1016/j.suscom.2023.100928

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Abstract

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Low-precision computing has emerged as a promising technology to enhance performance in modern applications like deep neural network training and scientific computing. However, most existing circuits and systems are tailored to a single type of half-precision format, such as FP16 or BFloat16. In light of this limitation, this paper introduces the design of a multi-format floating-point multiplier capable of supporting a wide range of halfprecision formats, including both their signed and unsigned versions. Our design emphasizes high reconfigurability, allowing it to adapt to the required dynamic range and precision. Moreover, experimental results showed that the introduced unsigned versions of the half-precision floating-point formats resulted in improved circuit parameters and energy consumption.

Keywords:

Floating-point multiplier

Low-precision computing

Energy-efficient arithmetic circuits

IEEE FP16

BFloat16

An efficient multi-format low-precision floating-point multiplier

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