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An Efficient Ring Polynomial Multiplication Accelerator for Homomorphic Encryption
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DOI：10.1109/TCSII.2023.3295614.png)
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Abstract
En 中文
Fully homomorphic encryption has become a key technique for solving the conflict between cloud services and privacy preservation. The most time-consuming step in homomorphic schemes is ring polynomial multiplication (RPM). Number theory transform (NTT) and Karatsuba algorithms are efficient to accelerate RPM, yet they are limited by the modulus operations and degrees of the polynomial. The systolic array is adopted for RPM processing recently. However, a modular reduction operation is required as post-processing which increases the overall delay. This brief has proposed a cyclic systolic array architecture without a dedicated reduction unit by re-routing the output of the systolic array for reusing, resulting in a 50% clock cycles saving of processing time. The corresponding FPGA implementation has a reduction of 72.9% and 33.8% when n=256 and n=1024 for equivalent area time product (eATP), respectively, therefore achieving an improved trade-off between performance and resource consumption.
Keywords:
Fully homomorphic encryption
RLWE
negative wrapped convolution
systolic array
FPGA
ATP
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