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An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems
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DOI：10.1109/TCSII.2025.3547997.png)
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Abstract
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As wireline communication links transition from 100 Gb/s to 200 Gb/s per lane, new and complex forward error correction (FEC) architectures have been adopted to achieve acceptably low bit error rates (BERs). Understanding how these architectures impact link performance under various channel conditions is essential. This brief presents a flexible platform for field-programmable-gate-array (FPGA)-accelerated time-domain simulations. The platform is capable of modeling wireline systems relevant to the upcoming 200 Gb/s Ethernet standard including multi-part links, concatenated FEC codes with convolutional interleaving and soft-decision inner-FEC decoding. This FPGA platform can accurately demonstrate post-FEC BERs at the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-11}$ </tex-math></inline-formula> level within a day of simulation time, a speed improvement by a factor of 10,000 over software-based simulation platforms.
Keywords:
BER
concatenated FEC
convolutional interleaving
ethernet
FPGA
multi-part link
pulse amplitude modulation (PAM)
soft decision
200Gb/s
wireline transceiver
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