.png){kind=icon}
.png){kind=icon}
Return
An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core
.png){kind=icon}
OA
AI
DOI：10.1109/ACCESS.2020.2991299.png)
.png){kind=icon}
.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
Versatile video coding (VVC) will be released by 2020, and it is expected to be the next- generation video coding standard. One of its enhancements is multiple transform selection (MTS) for core transform. MTS uses three different types of 2D discrete sine/cosine transforms (DCT & x2013;II, DCT & x2013;VIII and DST & x2013;VII) and up to $64\times 64$ transform unit sizes. With this schema, significant enhancements of the compression ratio are obtained at the expense of more computational complexity on both encoders and decoders. In this paper, a deeply pipelined high-performance architecture is proposed that implements the three transforms for sizes from $4\times 4$ to $64\times 64$ according to working draft 4 of the standard. The design has been described in very high-speed integrated circuit hardware description language (VHDL), and it has been prototyped in a system on a programmable chip (SoPC). It is able to process up to 64 fps & x0040;$3840\times 2.160$ for $4\times 4$ transform sizes. To the best of our knowledge, this is the first implementation of an architecture for VVC MTS supporting the $64\times 64$ size.
Keywords:
FPGA
hardware architecture
multiple transform selection
pipeline
SoPC
versatile video coding
AI Summary
Key information extracted from the uploaded paper, including a brief overview, abstract, background, key highlights, visual analysis, and future outlook.