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An in-Array Build-In Self-Test Scheme for Embedded SRAM Array
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DOI：10.1109/TCSII.2024.3375637.png)
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Abstract
En 中文
An in-array Build-In Self-Test (BIST) scheme is proposed for the embedded SRAM array. The linear feedback shift register (LFSR) is used to implement the pattern generator, and the single/multiple-input signature register (SISR/MISR) is used to implement the response compactor. The proposed BIST scheme only consumes half the number of transistors and area compared with the conventional LFSR/MISR BIST, and it is testable. The conventional BIST circuit outside the SRAM array is unnecessary if the proposed BIST scheme is applied. The proposed BIST scheme is able to implement various March sequences to test the other part of the memory array.
Keywords:
Built-in self-test
Generators
SRAM cells
Logic gates
Transistors
Discharges (electric)
Voltage
SRAM test
LFSR
SISR/MISR
in-array build-in-self-test
in-memory computing
Journal
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4.9
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8.8K
Citations:
2.5W