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Analog Convolution Circuit System Implemented With Capacitor Array Superposition
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DOI：10.1109/OJCAS.2026.3664009.png)
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Abstract
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This paper presents an architecture for analog convolution computing based on fundamental series-parallel capacitor configurations. The convolution results are digitized through a capacitance-difference-to-digital converter (CDDC), enabling efficient analog-to-digital conversion. Furthermore, an offset calibration mechanism is incorporated into the CDDC to compensate for offset-induced errors, thereby preserving the accuracy of AI model inference. The proposed architecture was evaluated on the MNIST and EMNIST datasets. With offset calibration enabled, the system achieved classification accuracies comparable to those of the ideal model. Therefore, the proposed system can be adapted to various semiconductor processes, facilitating the realization of analog convolution computing chips.
Keywords:
Convolution
Capacitors
Capacitance
Logic
Computer architecture
Voltage control
Vectors
Charge coupled devices
Calibration
Accuracy
Analog convolution
capacitance-difference-to-digital converter (CDDC)
calibration
multiplication and accumulation (MAC)
Journal
I
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2.4
Papers:
4.5K
Citations:
387
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Cited Papers