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APTPU: Approximate Computing Based Tensor Processing Unit
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DOI：10.1109/TCSI.2022.3206262.png)
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Abstract
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We propose an approximate tensor processing unit (APTPU), which includes two main components: (1) approximate processing elements (APEs) consisting of a low-precision multiplier and an approximate adder, and (2) pre-approximate units (PAUs) which are shared among the APEs in the APTPU's systolic array, functioning as the steering logic to pre-process the operands and feed them to the APEs. We conduct extensive experiments to evaluate the performance of the APTPU across various configurations and various workloads. The results show that the APTPU's systolic array achieves up to 5.2 x TOPSmm(2) and 4.4 x TOPS/W improvements compared to that of a conventional systolic array design. The comparison between the proposed APTPU and in-house TPU designs shows that we can achieve approximately 2.5 x and 1.2 x area and power reduction, respectively, while realizing comparable accuracy. Finally, a comparison with the state-of-the-art approximate systolic arrays shows that the APTPU can realize up to 1.58x , 2x , and 1.78x , reduction in delay, power, and area, respectively, while using similar design specifications and synthesis constraints.
Keywords:
Approximate computing
tensor processing units
machine learning hardware accelerator
systolic array
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