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Area-Efficient Multimode Encoding Architecture for Long BCH Codes
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DOI：10.1109/TCSII.2013.2281941.png)
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Abstract
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This brief presents a new area-efficient multimode encoder for long Bose-Chaudhuri-Hocquenghen codes. In the proposed multimode encoding architecture, several short linear-feedback shift registers (LFSRs) are cascaded in series to achieve the same functionality that a long LFSR has, and the output of a short LFSR is fed back to the input side to support multimode encoding. Whereas previous multimode architectures necessitate huge overhead due to preprocessing and postprocessing, the proposed architecture completely eliminates the overhead by exploiting an efficient transformation. Without sacrificing the latency, the proposed architecture reduces hardware complexity by up to 97.2% and 49.1% compared with the previous Chinese-remainder-theorem-based and weighted-summation-based multimode architectures, respectively.
Keywords:
Bose-Chaudhuri-Hocquenghen (BCH) encoder
linear-feedback shift register (LFSR) architecture
multimode
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