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Bayes2IMC: In-Memory Computing for Bayesian Binary Neural Networks

delete2025-01-01
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PRE
AI
P
Prabodh Katti
C
Clément Ruah
O
Osvaldo Simeone
B
Bashir M. Al‐Hashimi
B
Bipin Rajendran
DOI：10.1109/TCSI.2025.3543065delete
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Abstract

Abstract

En 中文
Bayesian Neural Networks (BNNs) generate an ensemble of possible models by treating model weights as random variables. This enables them to provide superior estimates of decision uncertainty. However, implementing Bayesian inference in hardware is resource-intensive, as it requires noise sources to generate the desired model weights. In this work, we introduce Bayes2IMC, an in-memory computing (IMC) architecture designed for binary BNNs that leverages the stochasticity inherent to nanoscale devices. Our novel design, based on Phase-Change Memory (PCM) crossbar arrays eliminates the necessity for Analog-to-Digital Converter (ADC) within the array, significantly improving power and area efficiency. Hardware-software co-optimized corrections are introduced to reduce device-induced accuracy variations across deployments on hardware, as well as to mitigate the effect of conductance drift of PCM devices. We validate the effectiveness of our approach on the CIFAR-10 dataset with a VGGBinaryConnect model containing 14 million parameters, achieving accuracy metrics comparable to ideal software implementations. We also present a complete core architecture, and compare its projected power, performance, and area efficiency against an equivalent SRAM baseline, showing a 3.8 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.6 \times $ </tex-math></inline-formula> improvement in total efficiency (in GOPS/W/mm2) and a 2.2 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.6 \times $ </tex-math></inline-formula> improvement in power efficiency (in GOPS/W). In addition, the projected hardware performance of Bayes2IMC surpasses most memristive BNN architectures reported in the literature, achieving up to 20% higher power efficiency compared to the state-of-the-art.
Keywords:
Bayesian neural networks
PCM
in-memory computing

Journal

I
ieee transactions on circuits and systems i: regular papers
IF:
0
Papers:
268
Citations:
0

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No organization information available