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bit-ReAAP: A Scalable and Memory-Efficient Processor for Bit-Level Reconfigurable Computing
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DOI：10.1109/tc.2026.3743101.png)
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Abstract
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Memory dominates the architecture design of domain-specific processors for accelerating deep learning workloads. In this work, by tailoring the memory hierarchy, we propose a customized memory subsystem to support extending reconfigurable computing to the bit-level within our domain-specific processor, named bit-ReAAP. Instead of hardware-managed caches, we adopt software-controlled scratchpads as on-chip local memories to provide low-latency operands in parallel while effectively hiding off-chip memory access latency. Guided by software-configured parameters, the quantized, mixed-precision (1~8-bit) operands are bit-packed into constant-width vectors according to specialized, software-defined memory layouts. To maximize memory bandwidth utilization, we incorporate dedicated vector address generation into the hardware to facilitate high-bandwidth streaming access for the bit-packed vectors. Through architectural customization, the proposed unified memory architecture provides a unified address space, enabling zero-copy data access between the host CPU core and the specialized coprocessor. A scalable vector architecture is proposed to implement the specialized coprocessor. By tightly coupling bit-serial operations with the customized memory subsystem, the proposed vector architecture scales two levels of parallelism for accelerating diverse layer-level workloads. Specifically, while hardware resources are organized into parallel vector lanes, this architecture dynamically adjusts the number of active lanes, and reconfigures the bit-width of the active lanes as 8-bit, 32-bit, or 64-bit, enabling multi-granular scalability. Simultaneously, we developed a domain-specific compiler that systematically schedules computation and memory access to saturate the specialized coprocessor. For evaluation, the bit-ReAAP processor is fully implemented on an embedded FPGA platform. By significantly improving memory efficiency and hardware utilization at bit-level granularity, bit-ReAAP demonstrates high scalability and memory efficiency for deploying flexibly quantized DNNs.
Keywords:
Domain-specific processor
memory hierarchy customization
mixed-precision operands
scalable vector architecture
reconfigurable computing
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