Cache coherence in intelligent memory system

doi:10.1109/TC.2003.1214343

Cache coherence in intelligent memory system

2003-07-01

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DOI：10.1109/TC.2003.1214343

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The Active Pages model of intelligent memory can speed up data-intensive applications by up to two to three orders of magnitude over conventional systems. A fundamental problem with intelligent memory, however, arises when data cached by the processor is modified by tic in the merry. The Active Page model inherently limits sharing, keeping coherence tractable, but exacerbates saturation problems. we first present a hybrid snoopy/directory protocol for use in Active Pages. Limited sharing allows for a tow-latency, tow-bandwidth hybrid protocol. A transparent remapping mechanism is added for efficient caching. On smaller data sizes, explicit flushing and hardware coherence exhibit similar performance, but hardware coherence is easier to program and uses less bandwidth. Finally, we examine SMP multiprocessor systems to mitigate saturation effects. As the number of threads increases, the bandwidth needs increase, making hardware coherence even more attractive.

Keywords:

intelligent memory

merged DRAM logic

cache coherence

Cache coherence in intelligent memory system

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