arrow
Return

Can Electro-Mechanical Stress Enable Effective Majority Logic Implementations?

delete2026-01-01
delete0
PRE
AI
A
Arne Van Zegbroeck *
E
Emma Van Meirvenne
P
P. Anagnostou
F
Florin Ciubotaru
C
Christoph Adelmann
S
Said Hamdioui
S
Sorin Cotöfană
DOI:10.1109/OJNANO.2026.3661648delete
deleteOriginal
deleteOriginal request for help
deleteShare
deleteSave
Abstract

Abstract

En 中文
Theoretically speaking, Majority logic, originally proposed in the $ <^>{\prime }70s$, enables more compact and efficient arithmetic implementations than the conventional Boolean counterpart. Nonetheless, CMOS technology based Majority logic realizations remain challenging, as standard transistor-based approaches are unable to directly exhibit majority behavior. However, recent exploration on beyond CMOS technologies created a resurgence of the interest in majority logic. In this work, we propose and analyze a novel approach towards the 3-input Majority gate (MAJ3) implementation by means of piezoelectric materials. By leveraging their intrinsic electromechanical properties, we convert the digital input signals into mechanical deformations, which are accumulated in a transfer layer. Subsequently, we transform the combined deformation back to the electric domain with a piezoelectronics element properly designed to perform majority functionality. We first present the underlying principles behind our proposal with a short introduction on majority logic, piezoelectronics, and the utilized simulation framework. Afterwards we introduce the proposed piezoelectric 3-input Majority gate (piezo-MAJ3) and strategies for optimizing its behavior and performance. We also detail the material parameters and structural design impact on device performance by utilizing both analytical discussion and physics-based simulations. Finally, we shortly highlight how our proposal can be directly integrated into CMOS circuits and compare the piezo-MAJ3 potential cost and performance with the ones of state of the art implementations. Our results indicate that when compared with its CMOS counterpart, the piezo-MAJ3 gate requires half the area, it is 7x faster, while reducing with 44% the energy consumption.
Keywords:
Logic gates
Logic
Transistors
Stress
Strain
Thin film transistors
Permittivity
Costs
CMOS technology
Zinc oxide
Piezoelectric devices
logic circuits
majority logic
beyond CMOS
numerical simulations
mechanical stress
voltage control

Journal

I
IEEE Open Journal of Nanotechnology
IF:
1.9
Papers:
4
Citations:
187

Organization

D
delft university of technology
Scholars:
3.0K
Papers: 1.4K
Citations: 0
I
interuniversity microelectronics centre
Scholars:
6.3K
Papers: 3.9K
Citations: 0