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Circuit reliability prediction based on deep autoencoder network
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DOI：10.1016/j.neucom.2019.07.100.png)
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Abstract
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As semiconductor feature size continues to decrease and the density of integration continues to increase, highly reliable circuit design is experiencing many challenges, including reliability evaluation, which is one of the most important steps in circuit design. However, faced with the very large scale of integrated circuits at present, traditional simulation-based methods are slightly inadequate in terms of computational complexity and do not apply to the circuits at the concept stage. To solve this problem, this paper presents a new prediction method for circuit reliability based on deep auto encoder networks. Firstly, we analyze and extract the main features associated with circuit reliability. Next, we construct an efficient method for data collection by combining the characteristics of the feature set with the requirements of deep auto encoder networks. Then, we build a deep auto encoder network model oriented to circuit reliability prediction in a supervised learning manner. Simulation results on 74-series circuits and ISCAS85 benchmark circuits show that although the accuracy of the proposed method is slightly lower than that of both the Monte Carlo (MC) method and the fast probabilistic transfer matrix (F-PTM) model, its time-space consumption is approximately constant on different circuits, and it is 102,458,469 times faster than the MC method, and approximately 4,383 times faster than the F-PTM model. Furthermore, the proposed method could be used to predict circuit reliability at the conceptual stage, and it is a very efficient approximation method that could greatly reduce the power consumption of the calculation. (C) 2019 Published by Elsevier B.V.
Keywords:
Logic circuit
Input vector
Feature set
Deep auto encoder network
Reliability prediction
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