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CMOS-compatible ferroelectric tunnel junctions integrate stochastic sampling and deterministic computing for image generation
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DOI：10.1038/s41467-026-72969-6.png)
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Abstract
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Recent progress in generative modeling has intensified the need for compact, energy-efficient hardware platforms. Yet, implementing image generation directly in hardware remains challenging due to the conflicting requirements of stochastic latent space sampling and deterministic decoding. Here, we show a unified hardware framework based on hafnium-oxide ferroelectric tunnel junctions (FTJs) that intrinsically support both functionalities within a single device array. Leveraging the CMOS- and VLSI-compatible fabrication of hafnia ferroelectrics, we realize dual-mode operation: random telegraph noise generation for controllable stochastic sampling, and high-fidelity vector–matrix multiplication enabled by non-volatile multi-level conductance states. Voltage and sampling-time tuning provide fine control over randomness and reliability, enabling high-quality image generation for tasks such as handwritten digit synthesis (MNIST) and high-resolution facial image generation (CelebA). Circuit-level demonstrations confirm stable performance over 105 cycles, surpassing prior hardware-based approaches and illustrating a viable route toward scalable, on-chip generative AI accelerators. AI image generation is limited by conflicting needs for stochastic sampling and deterministic decoding. Koo et al. present a ferroelectric tunnel junction array using controllable random telegraph noise and nonvolatile multilevel conductance to unify both functions, enabling high-quality digit and facial image synthesis.
Keywords:
ferroelectric tunnel junctions
stochastic sampling
deterministic computing
image generation
CMOS-compatible hardware
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