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Combining FPGA parallelism and machine learning for efficient image convolution
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AI
DOI：10.1088/2631-8695/ae655e.png)
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Abstract
En 中文
Recent advances in artificial intelligence and deep learning have transformed various fields relying on image processing, including autonomous vehicles, medical imaging, and advanced surveillance systems. A fundamental operation in these applications is image convolution, which requires both high accuracy and real-time performance, thereby demanding efficient acceleration techniques. Field programmable gate arrays (FPGAs) offer an attractive platform due to their reconfigurability and inherent parallelism. This paper proposes a scalable FPGA-based architecture for image convolution, using the Sobel filter as a case study. The proposed design exploits parallel processing by distributing computations across N parallel convolution kernels, while incorporating hardware-oriented optimizations in the Vitis HLS 2024 framework, such as loop unrolling, pipelining, and efficient use of on-chip memory. As a result, the architecture achieves a practical latency reduction that scales approximately with 1/N. Experimental results show that the proposed design reduces latency by up to 73% compared to existing architectures, while maintaining comparable resource utilization and consuming less than 0.4 W, demonstrating its suitability for low-power edge platforms. Furthermore, a machine learning ML-based prediction model is introduced to estimate the optimal number of parallel kernels for a given FPGA configuration. Six machine-learning models were evaluated, including decision tree, random forest (RF), support vector regression, K-nearest neighbors, gradient boosting, and XGBoost. Among them, RF and XGBoost achieved high accuracy on the full dataset and maintained strong performance under cross-family evaluation, demonstrating good generalization to unseen FPGA platforms. These results highlight the effectiveness of combining FPGA-based acceleration with ML for scalable and efficient design space exploration in real-time edge computing.
Keywords:
image convolution
edge detection
parallel processing
scalability
FPGAs
AI
ML
Journal
E
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