Competitive learning algorithms and neurocomputer architecture

doi:10.1109/12.707586

Competitive learning algorithms and neurocomputer architecture

1998-01-01

16

PRE

AI

H

H.C. Card *

G

Glenn Kenton Rosendahl

DOI：10.1109/12.707586

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Abstract

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This paper begins with an overview of several competitive learning algorithms in artificial neural networks, including self-organizing feature maps, focusing on properties of these algorithms important to hardware implementations. We then discuss previously reported digital implementations of these networks. Finally, we report a reconfigurable parallel neurocomputer architecture we have designed using digital signal processing chips and field-programmable gate array devices. Communications are based upon a broadcast network with FPGA-based message preprocessing and postprocessing. A small prototype of this system has been constructed and applied to competitive learning in self-organizing maps. This machine is able to model slowly-varying nonstationary data in real time.

Keywords:

computer architecture

parallel processing

neurocomputers

field programmable devices

artificial neural networks

competitive learning

self-organizing feature maps

Competitive learning algorithms and neurocomputer architecture

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