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Complementary Reconfigurable Field-Effect Transistor-Based Hybrid 6T SRAM Cell as a Multibit Dot-Product Engine In-Memory-Computing
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DOI：10.1109/JETCAS.2026.3690134.png)
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Abstract
En 中文
In-Memory Computing holds the promise to break the memory wall challenge; however, established memory device scaling cannot keep pace with growing architectural demands. We propose a complementary reconfigurable field effect transistor (CRFET) based hybrid 6T SRAM bitcell that holds potential for IMC architectures. established memory device scaling cannot keep pace with growing architectural demands. CRFET devices can be configured as n-type or p-type transistors during runtime using an additional programmable gate (PG) bias. Leveraging its CMOS compatibility, we combine conventional MOS transistors with CRFET transistors to propose a hybrid 6T bitcell. We exploit the current tuning capability of the CRFET device pass gate in the bitcell to achieve the multibit dot-product computations. We analyze and discuss the area efficiency through proposed mask designs, better noise margin, and energy efficiency through simulation using a Verilog-A-based spice model developed with the help of the Technology Computer-Aided Design (TCAD) simulations of a 7nm equivalent process design kit. We also demonstrate the robustness of the dot product engine (DPE) IMC in terms of output current and voltage characteristics, bitline non-linearities of multiple row arrays, and error percentage. The analysis shows that without area penalties compared to a conventional 6T memory array, it provides 24% better read noise margin and 18% average energy per operation efficiency versus conventional multibit DPE IMC implementations.
Keywords:
Dot product engine
hybrid SRAM
HSPICE model
in-memory computing
reconfigurable transistors
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