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Concatenated BCH and LDPC Coding Scheme With Iterative Decoding Algorithm for Flash Memory
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DOI：10.1109/LCOMM.2015.2391260.png)
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Abstract
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As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently proposed due to their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the extreme low error rate requirement of flash memory applications. Thus, concatenation of BCH and LDPC codes that strikes a balance between superb error correcting capability and low error floor becomes an alternative system structure. In this work, a modification of such concatenated coding system in Chen et al. [IEEE Commun. Lett., vol. 17, no. 5, pp. 980-983, May 2013] is proposed. Compared with the previous concatenated coding system via simulations, our design improves the error correcting capability in the waterfall region while keeps low error floor.
Keywords:
Low-density parity-check code
BCH code
concatenated code
flash memory
error floor
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