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CPU-GPU Heterogeneity Based Pipeline Parallel Architecture in Physical Layer Processing
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DOI：10.1007/978-3-032-10466-3_21.png)
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Abstract
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Efficient performance analysis and software-hardware decoupling are crucial for evaluating future communication technologies. However, current general-purpose processors fail to fully leverage the synergistic computational capabilities of the Central Processing Units (CPUs) and Graphics Processing Units (GPUs) when evaluating the performance of wireless protocol stacks, resulting in inefficient processing of compute-intensive tasks and an inability to meet the high-throughput demands of real-time scenarios. To address this issue, this paper proposes a pipeline parallel processing architecture based on CPU-GPU coordinated scheduling. During the pipeline parallel processing of multiple data frames, this architecture intelligently assigns computational tasks to the most suitable processing unit based on real-time load and processing unit structures, thereby improving processing efficiency, reducing power consumption, and enhancing overall system performance. Experimental results indicate that on the mid-range heterogeneous platform, the pipeline parallel architecture achieves a 172.15% throughput enhancement and a 63.26% latency reduction; on the high-end platform, it attains a 326.32% throughput enhancement and a 76.54% latency reduction, demonstrating robustness across hardware levels. These improvements alleviate the bottlenecks of existing Software-Defined Radio (SDR) simulation architectures.
Keywords:
CPU-GPU pipeline
Dynamic resource allocation
Energy efficiency
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