Cycle-Efficient LFSR Implementation on Word-Based Microarchitecture

doi:10.1109/TC.2012.14

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Cycle-Efficient LFSR Implementation on Word-Based Microarchitecture

2013-04-01

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Jui-Chieh Lin *

Sao‐Jie Chen

Yu Hen Hu

DOI：10.1109/TC.2012.14

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Abstract

En 中文

Cycle-efficient implementation of the linear feedback shift register (LFSR) algorithm on a word-based microarchitecture is investigated. This work examines an algorithm transformation method, called term-preserving look-ahead transformation (TePLAT), that transforms the bit-serial LFSR algorithm into a bit parallel format while maintaining the overhead of the original LFSR algorithm. Detailed implementation methodologies as well as extensive simulation results are presented. We apply TePLAT to 25 commonly used LFSRs and test the resulting parallel formulations on two popular word-based microprocessor development platforms: a Texas Instrument C6416 Code Composition Simulator and an ARM-9 Simulator. In all 25 cases, TePLAT transformed LFSR formulations consistently achieve much higher throughput than those of a naive implementation and a traditional look-ahead transformation-based implementation.

Keywords:

Linear feedback shift register

iteration bound

vector processing

look-ahead transformation

software defined radio

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