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Data Interface Buffer Compensation Scheme for Fast Calibration

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Abstract

Abstract

En 中文
Microprocessors and FPGAs need to enable simpler and compact platforms via integration of self-contained test and training circuits, training of data interface buffers for process and temperature variation being a prime example. This paper studies package embedding of resistors for buffer tuning and presents a scheme to utilize a single resistor to train a large number of buffers without increase in latency. Using SNR analysis, transient noise simulations and the consequent filtering latencies it is shown that embedding the compensation resistor on the package reduces the calibration time by 5 mu s while also reducing the filter size by a factor of 10.
Keywords:
Battery life
Buffer Tuning
Calibration Noise
Compensation Resistors
Passive Embedding
Power States

Journal

P
Proceedings of the Eighteenth International Symposium on Quality Electronic Design
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0
Papers:
4
Citations:
0

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