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DCT hardware structure for sequentially presented data

delete2001-11-01
delete3
PRE
AI
T
T.C. Tan
G
Guoan Bi *
Y
Yonghong Zeng
H
Han Tan
DOI：10.1016/S0165-1684(01)00113-Xdelete
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Abstract

Abstract

En 中文
This paper shows that a fast DCT algorithm is mapped into a hardware structure that consists of log(2) N modules. Such a hardware structure can be used for bit-serial word-serial or word-serial bit-parallel implementation. Compared to other methods of hardware implementation, the proposed one provides a naturally interface with sequentially presented input data, achieves a high utilization of hardware, requires a low processing latency and has a modular architecture that can be extended to support different transform sizes. (C) 2001 Elsevier Science B.V. All rights reserved.
Keywords:
discrete cosine transform
bit-serial processing
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Key information extracted from the uploaded paper, including a brief overview, abstract, background, key highlights, visual analysis, and future outlook.

Journal

Signal Processing cover
Signal Processing
IF:
3.6
Papers:
9.9K
Citations:
1.7W

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