DDMP's: Self-timed super-pipelined data-driven multimedia processors

doi:10.1109/5.740021

DDMP's: Self-timed super-pipelined data-driven multimedia processors

1999-01-01

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DOI：10.1109/5.740021

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This paper describes the world's first commercial data-driven multimedia processors (DDMP's), developed jointly by Osaka University, Kochi University of Technology, and Sharp Corporation. The data-driven principle underlying the structure of these processors was realized in a superpipelined implementation, which was in turn based on a self-tinted clocking scheme. This design made it possible to realize single chip DDMP's capable of executing tens of billions of signal processing operations per second with power consumption as low as 2 W. In terms of operations per watt, the processors exhibit threefold to tenfold improvement over conventional sequential digital signal processors (DSP's). The structure of this paper is as follows: 1) a brief introduction to the data-driven processing principle; 2) a detailed description of elementary modules for the realization of self-timed pipeline microprocessors; and 3) a description of the DDMP's developed thus far in the research project, which has continued for more than a decade. Also outlined here are the numerous advantages, in terms of both function and power consumption, of the self-timed pipeline over its synchronous counterparts. Commercially available DSP-oriented asynchronous data-driven processors and their practical applications to consumer appliances such as digital TV receivers are discussed; some programming examples are provided.

Keywords:

asynchronous pipeline

BOPS

consumer appliances

data driven

dataflow

diagrammatic program language

digital signal processing

low power consumption

self-timed

VLSI processors

DDMP's: Self-timed super-pipelined data-driven multimedia processors

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