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Design Approaches for Efficient Parallel Pseudo-Random Ternary Sequence Generation
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DOI：10.1109/TCSI.2025.3624649.png)
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Abstract
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A pseudo-random ternary sequence (PRTS) generator is essential for high-speed serial interfaces, as three-level pulse amplitude modulation (PAM-3) is increasingly adopted in recent standards such as USB4. To support high data rates, PRTS generation usually requires a high degree of parallelization. However, increased parallelism introduces critical hardware challenges, motivating the need for optimal hardware design. This paper introduces a novel design methodology that applies recursive and reverse recursive substitution to optimize the transition matrix along with simplified modulo-3 operators, thereby reducing computational overhead and improving hardware efficiency. The proposed design supports generating multiple sequence lengths by sharing hardware, allowing a single generator to handle different patterns with minimal overhead. In addition, PRTS checker functionality is embedded within the generator, enabling compact and fully integrated BIST capabilities. Fabricated in a 28-nm FDSOI process, the design provides up to 166.2 Gbps bandwidth with a power consumption of 6.16 mW, while only occupying 0.006 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. This work provides a scalable and efficient solution for PRTS generation in high-speed interfaces utilizing PAM3.
Keywords:
Pseudo-random ternary sequence (PRTS)
pseudo-random binary sequence (PRBS)
pseudo-random sequences
built-in self-test (BIST)
USB4
GDDR7
three-level pulse amplitude modulation (PAM-3)
transceiver
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