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Design of multiple-valued logic gates using gate-diffusion input for image processing applications
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DOI：10.1016/j.compeleceng.2018.05.019.png)
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Abstract
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In this work, unique characteristics of carbon nano-tube field effect transistor (CNTFET) are used to propose a universal cell with a simple architecture based on the binary modified gate-diffusion input (m-GDI) method for designing fundamental gates in the voltage-mode multiple-valued logic (MVL) with any arbitrary number of logic levels for processing at nano-scales. The results of the simulations confirm more energy-efficiency, larger noise margins and lower sensitivity of the proposed designs in different logic levels as compared with the state-of-the-art designs. The effects of the process, voltage and temperature (PVT) variations are extensively evaluated by Monte-Carlo simulation. According to the results, the proposed designs are robust against PVT variations and noise. The proposed structure is applied to the MVL-based image processing. The results show that the output images of the proposed MVL-based inexact gates have an appropriate quality in compare with the images generated by the other similar exact gates.
Keywords:
Gate-diffusion input (GDI) technique
Carbon nano-tube (CNT) field effect transistor (CNTFET)
Multiple-valued logic (MVL)
Process voltage and temperature (PVT) variations
Noise margin
Image processing
Peak signal-to-noise ratio (PSNR)
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