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Development process for clusters on a reconfigurable chip
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DOI：10.1016/j.compeleceng.2011.09.006.png)
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Abstract
En 中文
Reconfigurable MPSoCs (Multiprocessor System-on-Chip) could be viable for certain applications niche where the flexibility of FPGAs (Field-Programmable Gate Array) and software is needed, and a small number of units dismiss other silicon options. However, their design complexity is very high, and raises additional problems, i.e. the definition of a suitable programming model, an efficient memory organization, and the need for ways to optimize application performance. In this paper, we propose a complete development process, which addresses these problems by complementing the current SoC (System-on-Chip) development process with additional steps to support parallel programming and software optimization. This work explains systematically problems and solutions to achieve a FPGA-based MPSoC following our systematic flow and offering tools and techniques to develop parallel applications for such systems. (c) 2011 Elsevier Ltd. All rights reserved.
Keywords:
PERFORMANCE
OPENMP
TOOL
Journal
C
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