DieCARE: Diekill-Correct ECC for HBM Reliability Without Additional Dies

Yesin Ryu

doi:10.1109/tc.2026.3703497

DieCARE: Diekill-Correct ECC for HBM Reliability Without Additional Dies

2026-06-15

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DOI：10.1109/tc.2026.3703497

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As High Bandwidth Memory (HBM) continues scaling to address the demands of data-intensive workloads and AI-driven applications, ensuring resilience against increasingly frequent memory faults has become critical. DieCARE introduces a novel memory architecture co-designed with an innovative Error Correcting Code (ECC) scheme to enable die-level fault tolerance without requiring additional dies. It strategically distributes data and ECC check bits across multiple dies, leveraging advanced ECC techniques with flexible symbol layouts to optimize error correction capability, latency, and area efficiency. System-level evaluations demonstrate that DieCARE reduces memory Failure In Time (FIT) rate by $\mathbf{12,000}\boldsymbol{\times}$ , while maintaining an extremely low Silent Data Corruption (SDC) rate. These reliability improvements translate into increased system availability, yielding substantial benefits for large-scale computing systems.

Keywords:

Reliability

HBM

ECC

die-level fault tolerance

DieCARE: Diekill-Correct ECC for HBM Reliability Without Additional Dies

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