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DS-CDMA Implementation With Iterative Multiple Access Interference Cancellation
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DOI：10.1109/TCSI.2012.2215784.png)
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Abstract
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In this paper an implementation of iterative joint detection for multiple access interference using direct-sequence code-division multiple-access (DS-CDMA) is presented. Results for multiple field programmable gate array (FPGA) platforms and multiple technology nodes for synthesized application specific integrated circuits (ASIC) are presented. The joint detection is performed using a generalized version of interleave-division multiple-access (IDMA) known as partition spreading (PS) CDMA. Decoding is performed using iterative methods from turbo and sum-product decoding. The synthesized ASIC system demonstrates a maximum aggregate throughput of 197 Mb/s for a fully loaded 50-user system, while the implemented FPGA 50-user system has a maximum aggregate throughput of 119 Mb/s.
Keywords:
Digital circuits
direct-sequence code-division multiple access
field programmable gate arrays
interference cancellation
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