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DSP-Reduced Reconfigurable Processor Design for Memory-Based FFT
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DOI：10.1002/cta.70405.png)
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Abstract
En 中文
The implementation flexibility of mixed-radix fast Fourier transform (FFT) enables dynamic radix combinations for multi-standard communication systems. However, conventional mixed-radix FFT designs exhibit computational resource redundancy when simultaneously supporting butterfly units of multiple radices, which results in suboptimal hardware resource utilization. This paper proposes a reconfigurable mixed-radix FFT processor incorporating an innovative reconfigurable butterfly unit design supporting radix-2/3/5 FFT operations and a multi-path parallel conflict-free access method. The redesigned butterfly unit enhances hardware resource efficiency through functionally heterogeneous architecture while eliminating access conflicts. Implemented and verified on a Xilinx XC7Z020CLG400-2 FPGA platform, comprehensive testing of the FFT processor system demonstrates a 25% reduction in digital signal processor (DSP) consumption and a 26% improvement in computational efficiency versus state-of-the-art memory-based FFT processors.
Keywords:
butterfly unit
conflict-free access
DSP reduction
fast Fourier transform (FFT)
mixed-radix
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