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E-Mode GaN p-MOSFET Based on a Double Heterostructure with a Buried Back Gate Achieving Low Subthreshold Slope and Zero Hysteresis
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DOI：10.1021/acsaelm.6c00225.png)
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Abstract
En 中文
In this study, an approach and device structure to improve threshold voltage VTH stability and subthreshold slope (SS) of GaN p-MOSFET are reported. Based on the p-GaN/AlN/AlGaN/AlN/GaN double heterostructure, the proposed enhancement-mode (E-mode) GaN p-MOSFET features an intrinsic buried back gate (BBG) by employing the 2DEG channel at the buried AlGaN/AlN/GaN heterojunction. The BBG effectively mitigates the defective MOS-gate interface issue and endows the device with excellent VTH stability (ΔVTH < 0.2 V) within a large gate swing at room and high temperatures (25–150 °C). Moreover, benefiting from the BBG-enhanced gate-to-channel controllability, a high ION/IOFF current ratio of ∼108 and an ultralow SS of 85.6 mV/dec are obtained. Besides, the device with a dual-gate structure delivers a high VTH of –2 V with excellent pinch-off at zero gate bias showing a decent E-mode operation.
Keywords:
Interfaces
Nitrides
Power
Stability
Thermodynamic properties
GaN
p-MOSFET
back gate
enhancement mode
subthreshold slope
threshold voltage stability
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4.7
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5.0K
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1.4W
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