Efficient algorithm and architecture for post-processor in HDTV

doi:10.1109/30.663726

Efficient algorithm and architecture for post-processor in HDTV

1998-02-01

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DOI：10.1109/30.663726

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To display high quality images on the monitor screen in HDTV, the processed image data must be converted into the form appropriate for the realtime display. This paper presents the efficient algorithm and architecture for the post-processor, which has four functions. The first function is to remove blocking effect in HDTV images, and the second function is to convert the scan formats appropriate for the display. The third function is to convert the YUV format image signals into the RGB format signals. The final function is the gamma correction for better quality images. To reduce the size of a memory, a memory is partitioned into many memory banks. Also, to improve the operation speed, a pipelined parallel architecture and a memory scheduling technique are adopted. Therefore this architecture is very fast and uses small size memory banks, and this makes it possible to realize a real-time signal processor.

Efficient algorithm and architecture for post-processor in HDTV

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