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Efficient Circuit for Parallel Bit Reversal
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DOI：10.1109/TCSII.2015.2504943.png)
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Abstract
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Bit reversal is an essential part of the fast Fourier transform (FFT). However, compared to the amount of works on FFT architectures, far fewer works are dedicated to bit-reversal circuits until recent years. In this brief, the minimum latency and memory required for calculating the bit reversal of continuous-flow parallel data are formulated. The formulas are generic for all power of two parallelism, including the serial bit reversal. Furthermore, an efficient circuit for calculating the parallel bit reversal is proposed. The circuit not only achieves the lowest latency but also uses the minimum memory. This is achieved by breaking the bit-reversal permutation into two subpermutations, which are implemented by a sub-bit-reversal module and a group of P buffer banks. In addition, two commutators are adopted to access the P buffer banks efficiently. The proposed circuit is simple and efficient for reordering the output samples of parallel pipelined FFT processors.
Keywords:
Bit-reversal circuit
fast Fourier transform (FFT)
parallel pipelined architecture
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