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Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes
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DOI：10.1109/TCSI.2010.2046196.png)
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Abstract
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This paper addresses decoder design for nonbinary quasicyclic low-density parity-check (QC-LDPC) codes. First, a novel decoding algorithm is proposed to eliminate the multiplications over Galois field for check node processing. Then, a partially parallel architecture for check node processing units and an optimized architecture for variable node processing units are developed based on the new decoding algorithm. Thereafter, an efficient decoder structure dedicated to a promising class of high-performance nonbinary QC-LDPC codes is presented for the first time. Moreover, an ASIC implementation for a (620, 310) nonbinary QC-LDPC code decoder over GF(32) is designed to demonstrate the efficiency of the presented techniques.
Keywords:
Decoder architecture
extended min-sum (EMS)
fast Fourier transform (FFT) belief propagation (BP)
Min-Max decoding
nonbinary quasicyclic low-density parity-check (QC-LDPC) codes
very large scale integration (VLSI)
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