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Efficient Hardware Implementation of Partial Response Equalization With Reduced-State Sequence Estimation Decoder and Blind Adaptation Using Delay Zero Forcing Algorithm for DCI
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DOI：10.1109/JLT.2026.3659139.png)
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Abstract
En 中文
With the growing demand for data center interconnect (DCI) capacity, partial response equalization (PRE), employing either a 1/(1+D) decoder or an maximum likelihood sequence estimation (MLSE) decoder, has emerged as an effective solution to address the critical bandwidth limitations restricting system transmission rates. However, the 1/(1+D) decoder suffers from its inherent feedback loop and error propagation, while the MLSE decoder is limited by its high hardware complexity. Meanwhile, blind adaptive algorithms also encounter bottlenecks in PRE. Severe bandwidth limitations significantly impact the blind convergence of the decision-directed least mean squares (DD-LMS) algorithm. Additionally, PRE adversely affect the traditional zero forcing (ZF) algorithm, leading to extended convergence times. In this paper, we propose and experimentally demonstrate a hardware implementable PRE with reduced-state sequence estimation (RSSE) decoder and delay-ZF algorithm in a real-time 80 Gbps four-level pulse amplitude modulation (PAM-4) intensity modulation/direct detection (IM/DD) transmission system based on an FPGA chip. Statistical results from various transmission scenarios indicate that the RSSE decoder achieves BER performance comparable to that of the full-state MLSE decoder, while reducing the implementation complexity by up to 75%. Moreover, experimental results demonstrate that under blind equalization, employing the delay-ZF algorithm to update the PAM-7 targeted FFE reduces the blind convergence time by up to 55.8% and 74.9% compared to the traditional ZF and DD-LMS algorithms, respectively.
Keywords:
Blind equalization
delay-ZF
IM/DD
partial response
real-time
RSSE decoder
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