Efficient Majority Logic Parallel-Prefix Adder Design

C. Efstathiou

doi:10.1109/ACCESS.2025.3639651

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Efficient Majority Logic Parallel-Prefix Adder Design

2025-01-01

C. Efstathiou

Ioannis Kouretas

Paris Kitsos

DOI：10.1109/ACCESS.2025.3639651

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Abstract

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Emerging beyond CMOS technologies such as quantum-dot cellular automata (QCA), resistive RAM crossbars, spin-torque devices, and single-electron transistors implement only the three-input majority gate (MG) and the inverter as primitive operations. Therefore, efficient arithmetic designs are required for adder architectures implemented entirely in MG logic. This article introduces a methodology that maps any conventional parallel-prefix adder directly to an MG network, reformulating the sum computation so that the parallel-prefix tree is simplified. Based on the proposed technique, two topologies are introduced namely the Simplified Kogge–Stone (SKS) and Simplified Ladner–Fischer (SLF) adders. Both topologies utilise novel MG-based cells, and retain a critical-path depth of $\log _{2} n + 3$ MG delays, identical to their full-prefix counterparts. Analytical evaluation for 8- to 128-bit adders demonstrates that SKS reduces total MG count by 22.7%–38.5% compared with the best majority-logic Kogge–Stone counterparts, while SLF exhibits 5.9%–25.1% savings over majority-logic Ladner–Fischer designs, without increasing inverter overhead. The proposed methodology derives lower-complexity, high-throughput adders that are directly mapped on majority-gate nanotechnologies and offers a scalable procedure toward arithmetic building blocks for beyond-CMOS systems.

Keywords:

Parallel-prefix adders

majority logic

emerging nanotechnologies

arithmetic circuits

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