Efficient Memory/Bandwidth Utilization Data Compression Techniques in Wireless Data Processing SoC Systems

Silpa Rose Mary

doi:10.1109/TC.2026.3672461

Efficient Memory/Bandwidth Utilization Data Compression Techniques in Wireless Data Processing SoC Systems

2026-03-11

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DOI：10.1109/TC.2026.3672461

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To address growing wireless data processing demands in telecommunications and radar sensors, heterogeneous multiprocessor systems-on-chip (MPSoC) integrating programmable processors and hardware accelerators are increasingly being utilized. As the number of multiple-input multiple-output (MIMO) elements to process data increases in telecommunications and radar system on chips (SoCs), computational complexity and area of these SoCs also grows. Use of MIMO technology also increases the volume of data transfer across the interconnects and also data storage requirements in on-chip memories of the MPSoCs. Data compression is an important way to reduce memory sizes, data transfer time, and communication bandwidth requirements in wireless data processing SoCs. In this article, we focus on efficient memory and bandwidth utilization data compression techniques for wireless data processing SoCs with applications in telecommunications and automotive radars. To this end, our contribution is twofold: First, we present a comprehensive literature review of both lossy and lossless compression techniques playing a critical role in reducing bandwidth utilization across SoC interconnects and minimizing on-chip memory usage. We provide a classification of the use of compression techniques utilized for data compression, and also propose a comprehensive taxonomy of compression techniques for wireless data processing SoCs. We make the case that, although automotive radar SoCs currently utilize data compression techniques to save on-chip memory sizes, compression during in-phase and quadrature (IQ) data transfers from the front-end to the baseband is now essential for MIMO radars. This is due to the large number of receive processing chains being incorporated in these radars to improve their resolution to meet the stringent requirements of autonomous driving. Our second contribution is to design data compression for automotive radar IQ data. Using real radar data collected by us, via the Texas Instruments (TI) AWR1642 radar SoC, we present radar IQ data analysis. We also present two radar data compression techniques for radar data transfer and show that block floating point (BFP) compression performs better than block scaling compression (BSC). Our results show that the automotive radar IQ data can be compressed 50% without degrading the radar detection performance.

Keywords:

Data compression

memory

bandwidth

SoC

BFP

BSC

cellular networks

radar sensor

6G

MIMO

wireless communication

lossy data compression

lossless data compression

Efficient Memory/Bandwidth Utilization Data Compression Techniques in Wireless Data Processing SoC Systems

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