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Efficient On-Chip Replication
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DOI：10.1109/ACCESS.2024.3484013.png)
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Abstract
En 中文
As resilience challenges evolve, namely in safety- and security-critical environments, the demand for cost-efficient, automated and unattended fault and intrusion tolerance (FIT) grows. However, current on-chip solutions typically target only accidental faults and rely on some form of application-specific redundancy, a single-point-of-failure (SPoF) management software layer or synchrony-reliant protocols. Plus, they are often performance heavy and costly for the emerging tightly-coupled systems in terms of area and power consumption. In this paper, we investigate novel ways to apply high-performance FIT by using replication of a lightweight agreement protocol, iBFT, executed with the aid of hardware trusted-trustworthy memory tag accelerators, to avoid misuse of critical operations and SPoFs. We introduce an FPGA-based implementation of iBFT under two fault models, evaluate their performance, area usage, and power consumption on a Zynq ZC702 FPGA and compare it with other state-of-the-art protocols. Additionally, we implement and evaluate a software-based emulation of a potential microcode implementation.
Keywords:
Protocols
Computer crashes
Redundancy
Proposals
Clocks
Safety
Memory management
Measurement
Fault diagnosis
Intrusion detection
Resilience
Fault and intrusion tolerance
hardware
resilience
systems architecture
Journal
IF:
3.6
Papers:
9.8W
Citations:
29.4W