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Efficient Register-Balancing for Masked Hardware
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DOI：10.1109/LES.2025.3600586.png)
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Abstract
En 中文
Power side channel attacks (PSCAs) are a significant threat to secure cryptographic processors. Masking is an algorithmic countermeasure against PSCAs. During masking, the insertion of registers at designated locations according to the masking scheme is pivotal to ensure glitches in hardware do not effect the PSCA security. Such an insertion should be followed by proper insertion of balancing registers to ensure equal number of registers in all parallel paths of the design. This is called register balancing (RB). An RB procedure should also ensure minimum latency to meet the time constraints of cryptographic workloads. Previously, RB has been carried using a retiming-based approach which involved finding a correct set of retiming labels via solving a set of constraints on these labels, with a time complexity of O(V(V + E)). This work presents a faster RB approach with a time complexity of O(V + E). The new RB approach used to generate masked AES-256 Canright's and PRESENT S-boxes demonstrated upto 28x faster automated synthesis of masked hardware over existing approaches.
Keywords:
Masking
power side channel security
Masking
power side channel security
Journal
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2
Papers:
101
Citations:
696